1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Related Art
There has been an FBC memory device as a semiconductor memory device expected as a memory alternative to a 1T (Transistor)-1C (Capacitor) DRAM. The FBC memory device has an FET (Field Effect Transistor) formed to include floating bodies (hereinafter, also “bodies”) on an SOI (Silicon On Insulator) substrate. The FBC memory device stores data “1” or data “0” based on the number of majority carriers accumulated in the bodies. For example, in an FBC including N-type FETs, a state of a large number of holes accumulated in the bodies is set as data “1”, and a state of a small number of holes accumulated in the bodies is set as data “0”. A memory cell storing the data “0” is called a “0” cell, and a memory cell storing the data “1” is called a “1” cell.
In recent years, a fin-FBC suitable for a fully depleted operation has been developed. The fin-FBC is disclosed in Japanese Patent Application Laid-open (JP-A) No. 2007-18588 (see FIG. 12), for example. Along with progress of downscaling the memory device, a gate length of the FBC becomes shorter. Decreasing the gate length brings about reduction of a difference between a threshold voltage (signal amounts) of the “0” cells and that of the “1” cells, and increases the number of fail bits. This is because a body region capable of accumulating a charge decreases. Along with the progress of downscaling the memory device, an operation voltage needs to be decreased. However, when the operation voltage is decreased, a difference between the number of holes in the “0” cells and that in the “1” cells becomes small, and consequently a difference between the threshold voltages becomes small. According to a fin configuration disclosed in JP-A No. 2007-18588, the downscaling cannot be performed while maintaining a signal difference.
Vertical transistors are used as FBCs in JP-A H8-064778 (FIG. 20), JP-A 2002-329795 (FIG. 10), JP-A 2003-86712 (FIG. 45B), and JP-A 2005-26366 (FIG. 3). In these FBCs, a first N-type region is provided above bodies, a second N-type region is provided below the bodies, and gates are provided on a side surface of the bodies. The first N-type region and the second N-type region are arranged in a direction orthogonal with a surface of a semiconductor substrate. Plural memory cells share the second N-type region provided on the semiconductor substrate. In this vertical configuration, parasitic resistance in the second N-type region becomes a problem. The side surface of the bodies on which the gates are provided (the surface of the bodies on which channels are formed) faces a bit line direction. In this configuration, when a width (thickness) of the bodies in a bit line direction becomes small, a short-circuiting occurs between electrodes due to a contact, and this has a problem of increasing a contact resistance.